Ferroelectric materials are composed of many randomly-distributed permanently polarized regions. Under the presence of an electric field, the regions with a polarization component in the direction of the electric field grow at the expense of the non-aligned regions so that a net polarization can result. If the electric field decreases, the polarization also decreases but at a slower rate so that even when the electric field becomes zero, a remnant polarization remains. This remnant polarization, existed under zero field condition (i.e., when power is turned off), is the basis of ferroelectric nonvolatile memory devices such as ferroelectric transistors.
The ferroelectric transistor is typically a ferroelectric-gate-controlled semiconductor field-effect transistor (FET), which employs a ferroelectric film in contact with a silicon substrate, and in which a proper polarization of the ferroelectric film can create an inversion layer in the silicon channel of the transistor. The basic ferroelectric-gate controlled field-effect transistor is a metal-ferroelectric silicon (MFS) FET. The term MFS represents the layers in the gate stack of the ferroelectric transistor, consisting a metal (M) gate electrode disposed on a ferroelectric (F) gate dielectric on the silicon (S) channel of the transistor.
However, effective transistor operation of the above MFS transistor is difficult to achieve due to the requirement of the ferroelectric/silicon interface. When a ferroelectric film is deposited directly on the silicon substrate, metals and oxygen from the ferroelectric layer may diffuse into the ferroelectric-silicon interface, creating interface trapped charges which affect the polarization of the ferroelectric film, and overall may make the operation of the ferroelectric transistor unstable. Further, since the thermal expansion coefficient and lattice structure of a ferroelectric film is not compatible with silicon, it is very difficult to form a high-quality ferroelectric film with a clean interface directly on the silicon substrate.
Among the various designs to improve the ferroelectric/silicon interface in ferroelectric memory devices by modifying the interface layer (gate dielectric, Schottky diode formation, conductive oxide), the option of conductive oxide interface layer is very promising since it does not have the drawbacks of a dielectric interface layer, and may not have the drawbacks of the metal interface layer of a Schottky diode formation. The conductive oxide interfacial layer may also improve the quality of the ferroelectric film and the operation of the ferroelectric transistor by possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem at the ferroelectric interface to improve the reliability of the ferroelectric transistor, and possible etch selectivity improving with other dielectric and metal films. Details of the novel ferroelectric transistor designs employ a conductive oxide, a conductive metal oxide, a doped conductive metal oxide or a semiconductor metal oxide interfacial layer are disclosed in co-pending application entitled “Conductive metal oxide gate ferroelectric memory transistor”, “In2O3 thin film resistivity control by doping metal oxide insulator for MFMox device applications”, and “Semiconductive metal oxide thin film ferroelectric memory transistor” of the same first inventors, hereby incorporated by reference.
Since the ferroelectric material is highly susceptible to degradation by impurity incorporation such as oxygen diffusion, the fabrication process of ferroelectric memory devices often includes an encapsulate layer to the ferroelectric material with silicon nitride being the most commonplace material for ferroelectric encapsulation. With the introduction of conductive oxide replacing the gate dielectric, the fabrication process of ferroelectric memory devices would require novel processes to ensure a proper fabrication of the transistor, in particular a selective etch process between the silicon nitride and the conductive oxide material.